Lecture 1
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Add diagram illustrating OCCAM code!!!
- a producer puts a value by sending the message give!value
- this is received by the buffer by the expression give?thebuffer[inindex]
- a consumer gets a value by sending the message signal!()
- the buffer receives this with the expression signal?any, and then replies by sending take!thebuffer[outindex]
- the consumer should then take this value by evaluating take?value

Or change names:
give/take/value

Lecture 2
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- Fix creation of new threads with runnable: add call to start()!
- add some sequence diagrams e.g., for clockthread example

Lecture 3
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- Question from Kretz -- algorithm for composing FSPs?

Lecture 4
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- minimal transfer protocol class -- show usage example!
  - slot class as alternative for transfer?

Lecture 5
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- Safety properties go too fast -- add more complex example?
  - add explanation: safety property generates a process in which
  all actions are always possible; the process specifies what is allowed;
  everything else leads to the error state
  - show a few examples
  - property SAFE = (heads -> SAFE | tails -> SAFE).
	ok, it is safe, but that is not what we are worried about
  - not clear why the process should be deterministic -- example?
  consider: P = (a->b->P|a->c->P) -- is a->b allowed ot not?!
  - property REPICK = (pick -> toss -> REPICK).
- Progress: ask how to fix the two coin example
  (eliminate trick coin; pick again after each toss)

Lecture 6
---------
- break the examples
- Can we force race conditions?
  - eg in BoundedCounterV1 -- eliminate public syncs


Lab 1
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* recompile labs to use different packages for solutions!
  [avoid problems reloading classes]
- Switch Rotator and Garden exercises
- Add hints to Rotator exercise
  - how many threads?
  - what is shared? what is synchronized?
  - who reads? who writes?
  - who waits? who notifies?

Lecture 7
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* race condition in Future implementation!
  - fix with own implementation
  - or recheck val_ in sync block
- overview of different approaches is unclear
  - what different problems do they solve?
  - how do they map to the basic scheme?
- need better examples for relays

Lecture 10
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- explain how RW_PROGRESS *lowers* priority of release ops!


Lab 2
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- Add figures to RW showing how to overlap times!

--- OTHER ---

CP updates
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- Add foils on how reentrant locks work! (seq diagram?)


